1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device having a memory cell array constituted by arranging a plurality of nonvolatile memory cells in a row direction and column direction respectively and arranging the plurality of word lines and the plurality of bit lines in the row direction and the column direction respectively in order to select a predetermined memory cell or memory cell group out of the arranged nonvolatile memory cells, more particularly relates to a nonvolatile semiconductor memory device having a variable resistive element in which a memory cell stores information in accordance with a change of electrical resistance.
2. Description of the Related Art
A technique is proposed in which one or more short electrical pulses is or are applied to a thin material having a perovskite structure, particularly a thin film or bulk constituted by a colossal magnetoresistance material (CMR) or a high temperature superconductivity (HTS) material to change electrical characteristics of the thin film or bulk. It is allowed that the electric field intensity and current density by the electrical pulses are large enough to change physical states of the material but the intensity and density respectively have a low enough energy unable to break the material and the electrical pulses have positive or negative polarity. Moreover, by repeatedly applying electrical pulses several times, it is possible to further change material characteristics.
The above prior art is disclosed in the specification of U.S. Pat. No. 6,204,139. FIGS. 8 and 9 are graphs respectively showing a relation between applied pulse number and resistance value in the prior art. More minutely, FIGS. 8 and 9 respectively show a relation between pulse number to be applied to a CMR thin film grown on a metallic substrate and resistance. In FIG. 8, a voltage pulse at an amplitude of 32 V and a pulse width of 71 ns is applied 47 times. Under the conditions, it is found from FIG. 8 that a resistance value changes by approx. one order of magnitude.
FIGS. 10 and 11 are graphs respectively showing a relation between polarity of applied pulse and resistance value in a prior art. FIG. 10 shows a resistance change state when applying voltage pulses of +12 V (positive polarity) and −12 V (negative polarity). In FIG. 11, applied voltages are +51 v and −51V and a resistance is measured after applying the pulse of each polarity. As shown in FIGS. 10 and 11, it is possible to decrease a resistance value by applying a positive-polarity pulse several times and thereafter increase the resistance value by applying a negative-polarity pulse (finally, resulting in a saturated state). It is considered that the above mentioned is applied to a memory device by bringing a state of applying a positive-polarity pulse into a reset state and a state of applying a negative-polarity pulse into a programming state.
The above conventional example discloses a case of arranging CMR thin films having the characteristic concerned like an array to constitute a memory array. In the case of the memory array concerned shown in FIG. 12, a bottom face electrode 26 is formed on a substrate 25 and a variable resistive element 27 and an upper face electrode 28 respectively constituting one bit are formed on the bottom face electrode 26. A wire 29 is connected to the upper face electrode 28 every bit to apply a programming pulse. Moreover, in the case of reading, a current corresponding to the resistance value of the variable resistive element 27 is read from the wire 29 connected to the upper face electrode 28 every bit.
However, because resistance changes of CMR thin films shown in FIGS. 10 and 11 are approx. two times, it is preferable that the resistance changes are larger in order to smoothly identify a reset state and a programming state when considering the fluctuation between elements. Moreover, the resistance changes are not suitable for a memory device in which a voltage to be applied to a CMR thin film is high and for which low voltage operations and low power consumption are requested.
Therefore, the applicant of this application was able to obtain a new characteristic by using PCMO (Pr0.7Ca0.3MnO3) which is a CMR material of an oxide having the perovskite structure same as the case of the prior art and containing manganese and thereby, applying one or more short electrical pulses. Specifically, by applying low voltage pulses of approx. ±5 V, a characteristic is obtained in which the resistance value of a thin film material is changed from hundreds of Ω up to approx 1 MΩ. Hereafter, the variable resistive element formed by the perovskite-structural oxide containing manganese is referred to as RRAM (Resistance control nonvolatile Random Access Memory) device.
Moreover, in addition to the above CMR thin film, there is a device which realizes a nonvolatile memory by using a magnetic field or heat instead of an electrical pulse, thereby changing electrical resistances to store information, and reading the information corresponding to the changed resistance value. For example, the following devices are proposed: MRAM (Magnetic RAM), OUM (Ovonic Unified Memory), and MTJ (Magnetic Tunnel Junction). A memory array device configuration using the above MTJ device is disclosed in Japanese Unexamined Patent Publication No. 2002-151661. FIG. 5 shows a memory cell configuration of this prior art only for a signal relating to reading.
However, in the case of the memory array shown in FIG. 12, a wire is connected to an electrode every bit and a programming pulse is applied through wire at the time of the programming operation. Moreover, at the time of reading, it is possible to evaluate the characteristic of a thin film material in order to read a current from a wire connected to an electrode every bit. However, there is a problem that it is impossible to raise the integration degree of a memory device. Furthermore, everything is controlled in accordance with a signal from the outside of a memory device in order to perform the programming operation, reading operation, and resetting operation. Hence, the memory device is not constituted as a conventional memory device capable of controlling the programming operation, reading operation, and resetting operation.
FIG. 13 is a circuit diagram schematically showing a configuration of a memory array closer to an actual device. A memory array 10 is constituted in which variable resistive elements Rc formed by using the above PCMO material are arranged like a matrix of 4×4. One-hand terminals of variable resistive elements Rc are connected to word lines W1 to W4 and the other-hand terminals of it are connected to bit lines B1 to B4. A peripheral circuit 32 is set adjacently to the memory array 10. A bit line selection transistor 34 is connected to each of the bit lines B1 to B4 to form a route to an inverter 38. A load transistor 36 is connected between the bit selection transistor 34 and the inverter 38. According to the above configuration, it is possible to program or read data in or from each variable resistive element Rc of the memory array 10.
In the case of the conventional memory array 10, memory operations can be performed at a low voltage. However, in the case of the programming and reading method, it is impossible to evaluate a correct current value at the time of the reading operation because a leak current to a memory cell adjacent to a memory cell to be accessed is generated. Moreover, because a leak current to an adjacent memory cell is also generated at the time of the programming operation, it may be impossible to perform a correct programming operation.
For example, in the case of the reading operation, it is possible to form a current route shown by an arrow A1 by connecting a power supply voltage Vcc to the word line W3, the bit line B2 to a ground potential GND, opening other bit lines B1, B3, and B4 and word lines W1, W2, and W4, and turning on a bit selection transistor 34a. Therefore, it is possible to read the resistance value of a variable resistive element Rca. However, current routes shown by arrows A2 and A3 are generated for the variable resistive element Rc adjacent to the variable resistive element Rca. Therefore, it is impossible to read the value of only the resistance of the variable resistive element Rca in a selected memory cell.
Therefore, it is possible to turn off the selection transistor of an unselected memory cell in an unselected row and thereby cut off a current route passing through an unselected variable resistive element formed in FIG. 13 and solve the above problems at the time of reading and programming by connecting a variable resistive element with a selection transistor in series and forming a memory cell as shown by the conventional example described in Japanese Unexamined Patent Publication No. 2002-151661.
A memory array when using an RRAM device as a variable restive element is described below. FIG. 6 is a circuit diagram of a memory cell 11 formed by connecting an RRAM device 2 and a selection transistor 3 in series, which has the same configuration as the memory cell in Japanese Unexamined Patent Publication No. 2002-151661 shown in FIG. 5. FIG. 7 shows a memory cell array configuration when using the memory cell 11. A plurality of RRAM devices is connected to bit lines BL1 to BL4 respectively.
First, the reading operation is described below. A bit selection transistor 4 is operated, for example, to apply 1.5 V to a bit line connected to a selected RRAM device so that a bias voltage can be applied to the bit line. At the same time, a word line connected to the gate of the selection transistor 3 (cell selection transistor) connected to the RRAM device 2 of a memory cell to be read is set to a high level (e.g. 7 V) by a word line driver 5 to turn on the cell selection transistor 3. Moreover, by setting the source of the cell selection transistor 3 (connected to common source lines SL1 and SL2) to a reference voltage (e.g. ground potential 0 V), a current route to the ground potential after passing through an RRAM device and the cell selection transistor 3 from the bias voltage of a bit line is generated. For an unselected memory cell, however, by setting the level of an unselected word line to a low level (e.g. ground voltage 0V) by the word line driver 5 and an unselected bit line to a low level or a high impedance (open state), a current route passing through a route other than the RRAM device of a memory cell selected by a reading bit line is disappeared. Under the above state, only a change of resistances of the selected RRAM device appears as a change of currents circulating through a bit line. By determining the current change by a reading circuit, it is possible to accurately read the information stored in a selected memory cell. As a result, it is possible to use a RRAM device as a memory device.
Then, the programming operation of the memory array is described below. In this case, it is assumed a case in which the resistance value of the RRAM device 2 is larger than a reference resistance value as a programming state and a case in which the resistance value is smaller than the reference resistance value as an erasing state. In this case, the bit line selection transistor 4 is operated so that a bias voltage can be applied to a bit line connected to the selected RRAM device 2, for example, to apply 3 V to the bit line. At the same time, a word line connected to the gate of the cell selection transistor 3 connected to the RRAM device 2 in which data is programmed is set to a high level (e.g. 7 V) by the word line driver 5 to turn on the cell selection transistor 3. Moreover, by setting the source (connected to common source lines SL1 and SL3) of the cell selection transistor 3 a predetermined value (e.g. ground potential 0 V), a current rouge is generated from the bias voltage of a bit line to the ground potential after passing through the RRAM device and cell selection transistor and data is programmed in a selected memory cell. For an unselected memory cell, however, by setting an unselected word line to a low level (e.g. ground potential 0 V), a current route from a selected bit line to the ground potential is not formed or data is not programmed.
Then, the erasing operation of the memory array is described for a case of block erasing which erases data in a lump every block. The bit selection transistors 4 are operated so that a bias voltage can be applied to all bit lines connected to RRAM devices in a block to apply the ground potential 0 V to the bit lines. At the same time, word lines connected to the gates of the cell selection transistors 3 connected to all RRAM devices are set to a high level (e.g. 7 V) to turn on the cell selection transistors. Moreover, by setting the sources (connected to common source lines SL1 and SL2) of the cell selection transistors 3 to a reference voltage such as 3 V, current routes are generated from the bias voltage of a common source lines to the bit lines having a ground potential 0 V through all cell selection transistors and RRAM devices in the block. According to the above operations, erasing operations of all memory cells in the block can be performed.
However, in the case of the above configuration in FIG. 7, not only a selected RRAM device but also an unselected RRAM device is connected to a selected bit line. Therefore, when applying a bias voltage to a bit line which is read for the reading operation, a voltage stress may be applied to the unselected RRAM device though a word line in an unselected row is kept at a low level. Moreover, even if the voltage stress is so weak that it can be ignored for one-time reading operation, the voltage stress may be repeatedly generated in the same memory cell. Therefore, resistance states of the RRAM device may be slowly changed for a long time. Furthermore, the same problem as the case of the reading operation may occur in the programming operation. Hence, it is requested to establish a higher-reliability data retention characteristic. It is requested to more securely avoid this problem because the RRAM device is a memory device for storing data by changing electrical resistances by an electrical stress and thereby, the RRAM device is more remarkable compared to the case of an MRAM device or OUM device for changing electrical resistances by a magnetic field or heat.